1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device having an internal power supply voltage down-converting circuit for converting down an external power supply voltage to produce an internal power supply voltage. More specifically, the present invention relates to a structure for reducing current consumption in an internal power supply voltage down-converting circuit upon a power-on.
2. Description of the Background Art
As a semiconductor memory device is increased in storage capacity and implemented with higher density and integration, transistor elements forming the same are refined or miniaturized. In order to guarantee the reliability of such refined transistor elements and reducing power consumption, an operating power supply voltage is preferably reduced. Such reduction of the operating power supply voltage guarantees the reliability of gate insulating films of MOS transistors (insulated gate field effect transistors) forming the semiconductor memory device while reducing power which is proportionate to the square of the operating power supply voltage V.
However, the semiconductor memory device must keep compatibility with those of earlier generations, and hence an external power supply voltage which is a system power source voltage for example is down-converted to a voltage level required in the interior.
FIG. 10 schematically illustrates the overall structure of a conventional semiconductor memory device. Referring to FIG. 10, the semiconductor memory device 1 includes an internal voltage down-converting circuit 1b which is connected with a power supply terminal 1a receiving an external power supply voltage EXTVcc for down-converting the same and generating an internal power supply voltage INTVcc on an internal power supply line 2, an internal power supply use circuit 1c using the internal power supply voltage INTVcc on the internal power supply line 2 for executing a prescribed function, and an external power supply use circuit id using the external power supply voltage EXTVcc on an external power supply line 3 which is connected with the external power supply terminal 1a. The external power supply use circuit id is connected with an external terminal 1e, for transmitting/receiving signals/data to/from an external circuit of the semiconductor memory device 1.
The internal power supply use circuit 1c uses the internal power supply voltage INTVcc on the internal power supply line 2 as one operating power supply voltage, for performing prescribed processing. This internal power supply use circuit 1c transmits/receives signals to/from the exterior of the device 1 through the external power supply use circuit 1d serving as an interface.
FIG. 11 illustrates an exemplary structure of the internal voltage down-converting circuit 1b shown in FIG. 10. Referring to FIG. 11, the internal voltage down-converting circuit 1b includes a comparator 10a for comparing a reference voltage Vref from a reference voltage generator circuit (not shown) with the internal power supply voltage INTVcc on the internal power supply line 2 when activated, a current source transistor 10b for activating the comparator 10a in response to activation of a voltage down-converting activation signal ACT, a drive transistor 10c formed by a p-channel MOS transistor which is connected between the external power supply terminal la and the internal power supply line 2 and receives an output signal of the comparator 10a at its gate, and a precharge transistor 10d formed by a p-channel MOS transistor for holding a gate potential of the drive transistor 10c at the level of the external power supply voltage EXTVcc in response to inactivation of the voltage down-converting activation signal ACT. The voltage down-converting activation signal ACT, the generation mode of which is described later, is brought into an active state of the external power supply voltage EXTVcc level during an activation period when the internal power supply use circuit 1c is brought into an operating state. The operation of the internal voltage down-converting circuit 1b shown in FIG. 11 is now briefly described.
When the voltage down-converting activation signal ACT is at a low level of an inactive state, the current source transistor 10b is in a nonconducting state, and the comparator 10a is in an inactive state. On the other hand, the precharge transistor 10d conducts in response to the inactive voltage down-converting activation signal ACT, to precharge the gate potential of the drive transistor 10c to the external power supply voltage EXTVcc level. The drive transistor 10c, whose gate and source potentials are identical to each other, is maintained in a nonconducting state. While the voltage down-converting activation signal ACT is in an inactive state, therefore, the internal voltage down-converting circuit 1b is in an inactive state to stop the operation of generating the internal power supply voltage INTVcc.
When the voltage down-converting activation signal ACT goes high to enter an active state, the current source transistor 10b conducts to form a current path for the comparator 10a, thereby activating the comparator 10a. The comparator 10a is formed by a differential amplifier circuit for differentially amplifying the internal power supply voltage INTVcc on the internal power supply line 2 and the reference voltage Vref (this structure is described later in detail). When the internal power supply voltage INTVcc is higher than the reference voltage Vref, the output signal of the comparator 10a goes high and the drive transistor 10c enters a nonconducting state. When the internal power supply voltage INTVcc is lower than the reference voltage Vref, on the other hand, the output signal level of the comparator 10a is reduced and the conductance of the drive transistor 10c is increased. The drive transistor 10c supplies a current from the external power supply terminal 1a to the internal power supply line 2 in accordance with its conductance, to increase the internal power supply voltage INTVcc.
The voltage down-converting activation signal ACT enters an active state when the internal power supply use circuit 1c using the internal power supply voltage INTVcc on the internal power supply line 2 operates. In this state, there is such a possibility that a large amount of operating current flows to the internal power supply use circuit 1c to reduce the internal power supply voltage INTVcc. In order to compensate for such reduction of the internal power supply voltage INTVcc in operation of the internal power supply use circuit 1c, the internal voltage down-converting circuit 1b is activated in accordance with the voltage down-converting activation signal ACT. In a non-operating state (standby state) of the internal power supply use circuit 1c, the internal power supply voltage INTVcc is not used but only an extremely small standby current (leakage current) is generated, and the internal power supply voltage Vcc is maintained at a substantially constant voltage level.
FIG. 12 illustrates an exemplary structure of the comparator 10a shown in FIG. 11. Referring to FIG. 12, the comparator 10a includes p-channel MOS transistors 10aa and 10ab forming a current mirror circuit which is connected with a power supply node 3a and supplies a current from the power supply node 3a, and n-channel MOS transistors 10ac and 10ad forming a comparator stage for comparing the internal power supply voltage INTVcc with the reference voltage Vref. The gate and the drain of the p-channel MOS transistor 10aa are connected with the drain of the n-channel MOS transistor 10ac. The gate and the drain of the p-channel MOS transistor 10ab are connected with the gate of the p-channel MOS transistor 10aa and the drain of the n-channel MOS transistor 10ad, respectively. The sources of the MOS transistors 10ac and 10ad are connected with the drain of the current source transistor 10b in common.
The internal power supply voltage INTVcc and the reference voltage Vref are supplied to the gates of the MOS transistors 10ac and 10ad, respectively. The connection node (drain) between the MOS transistors 10ab and 10ad is connected with the gate of the drive transistor 10c. The operation of the comparator circuit (including the comparator 10a and the current source transistor 10b) shown in FIG. 12 is now described.
When the voltage down-converting activation circuit ACT is at a low level, the current source transistor 10b is in a nonconducting state. Therefore, a path for a current flowing from the power supply node 3a to a ground node is cut off, so that this comparator circuit consumes only a leakage current of several .mu.A, for example, in this current source transistor 10b.
When the voltage down-converting activation signal ACT goes high, the current source transistor 10b conducts to form the path for feeding a current from the power supply node 3a to the ground node. When the internal power supply voltage INTVcc is higher than the reference voltage Vref, the conductance of the MOS transistor 10ac exceeds that of the MOS transistor 10ad, whereby the MOS transistor 10ac feeds a current in a larger quantity than the MOS transistor 10ad. The current flowing through the MOS transistor 10ac is supplied from the MOS transistor 10aa. The MOS transistors 10aa and 10ab form the current mirror circuit, and hence currents of the same quantity flow through the MOS transistors 10aa and 10ab (the MOS transistors 10aa and 10ab are identical in size to each other). The MOS transistor 10ad cannot entirely discharge the current supplied from the MOS transistor 10ab, and hence the gate potential of the drive transistor 10c is increased.
When the internal power supply voltage INTVcc is lower than the reference voltage Vref, on the other hand, the conductance of the MOS transistor 10ac is smaller than that of the MOS transistor 10ad, and hence the current flowing through the MOS transistor 10ac is smaller than that flowing in the MOS transistor 10ad. The current supplied through the MOS transistor 10ab is identical to that flowing through the MOS transistor 10ac, and hence the MOS transistor 10ad discharges the current supplied from the MOS transistor 10ab, the potential at the drain of the MOS transistor 10ad is reduced, and the conductance of the drive transistor 10c is increased in response.
This comparator circuit supplies a current to the internal power supply line 2 through the drive transistor 10c when the internal power supply use circuit 1c (see FIG. 10) uses the internal power supply voltage INTVcc, in order to compensate for reduction of the voltage level. A relatively large amount of operating current of several 10 mA, for example, flows in operation of the internal power supply use circuit 1c. In order to reliably compensate for reduction of the internal power supply voltage INTVcc caused by the large current consumption, the response speed of the comparator circuit is sufficiently increased. Therefore, a current of about several mA, for example, flows through the current source transistor 10b, to change the gate potential of the drive transistor 10c at a high speed in accordance with the difference between the internal power supply voltage INTVcc and the reference voltage Vref.
The internal voltage down-converting circuit 1b including the comparator circuit using the relatively large current is driven only at need, thereby reducing the current consumption.
FIG. 13 schematically illustrates the structure of a part generating the voltage down-converting activation signal ACT. Referring to FIG. 13, the voltage down-converting activation signal generator part includes an input buffer 15 receiving a row address strobe signal /RAS and a power-on detection signal ZPOR, and a voltage down-converting activation signal generator circuit 16 generating the voltage down-converting activation signal ACT in accordance with an output signal of the input buffer 15. The input buffer 15 includes a gate circuit 15a outputting a low-level signal when the row address strobe signal /RAS is at a low level and the power-on detection signal ZPOR is at a high level. The voltage down-converting activation signal generator circuit 16 includes an invertor 16b inverting the output signal of the gate circuit 15a.
The row address strobe signal /RAS defines the memory cycle of the semiconductor memory device 1, which is a DRAM (dynamic random access memory). When the row address strobe signal /RAS enters an active state of a low level, the DRAM uses the internal power supply voltage INTVcc in its interior, to start a memory cell selecting operation. The power-on detection signal ZPOR enters an active state of a high level when the external power supply voltage EXTVcc is applied and reaches a prescribed voltage level or enters a stable state. The power-on detection signal ZPOR is employed for inhibiting the internal circuit from operating when the external power supply voltage EXTVcc is at an instable voltage level. The operations of the voltage down-converting activation signal generator part shown in FIG. 13 are now described with reference to waveform diagrams shown in FIGS. 14 and 15.
With reference to FIG. 14, description is now made on an operation in case of starting to supply the external power supply voltage EXTVcc to the semiconductor memory device 1 while setting the row address strobe signal /RAS at a high level. Power is on at a time t1, to increase the voltage level of the external power supply voltage EXTVcc. An internal node of the comparator circuit is charged in response to the application of the power supply voltage EXTVcc, whereby a relatively large peak current is generated in the comparator circuit in accordance with the power-on. Referring to FIG. 14, a reference symbol 1c denotes the current flowing in the comparator circuit. After the internal node is charged to a prescribed level, the MOS transistors forming the semiconductor memory device 1 are maintained in prescribed states (initial states) respectively, and the potential of the internal node is increased in accordance with the increase of the external power supply voltage EXTVcc. In this state, the comparator circuit is in a stable state (initial state), and the current 1c of the comparator circuit is stable at a small value (the signal ACT is at a low level).
When the external power supply voltage EXTVcc reaches a prescribed voltage level at a time t2 to reduce the possibility of causing a malfunction of the internal circuit, the power-on detection signal ZPOR rises to a high level. Despite this rise of the power-on detection signal ZPOR, the row address strobe signal /RAS applied to the gate circuit 15a and the output signal of the gate circuit 15a are at high levels, and hence the voltage down-converting activation signal ACT outputted from the invertor 16b is at a low level. Therefore, the internal voltage down-converting circuit 1b maintains its inactive state, not to increase the current consumption.
At a time t3, the row address strobe signal /RAS falls to a low level in order to carry out a dummy cycle described later. In response to the fall of the row address strobe signal /RAS, the output signal from the gate circuit 15a falls to a low level, and the voltage down-converting activation signal ACT outputted from the invertor 16b goes high in response. In response thereto, the internal voltage down-converting circuit 1b is activated, so that the comparator circuit performs a compare operation. The current source transistor 10b of the comparator circuit conducts in accordance with the activation of the voltage down-converting activation signal ACT, whereby a relatively large current 1c flows in the comparator circuit.
When the external power supply voltage EXTVcc is applied while setting the row address strobe signal /RAS at H level, the voltage down-converting activation signal ACT is maintained at a low level and current consumption in the internal voltage down-converting circuit 1b is at a substantially ignorable degree in the power supply (leakage current level), as shown in FIG. 14.
With reference to FIG. 15, description is now made on an operation in case of supplying power while setting the row address strobe signal /RAS at a low level. The power is on at a time t1 while setting the row address strobe signal /RAS at a low level, to increase the voltage level of the external power supply voltage EXTVcc. Also in this case, the current 1c is instantaneously increased in order to set the internal node of the internal voltage down-converting circuit 1b in an initial state similarly to the case shown in FIG. 14, and thereafter returns to a normal state. Despite the low level of the row address strobe signal /RAS, the power-on detection signal ZPOR is at a low level, the output signal of the gate circuit 15a is at a high level, and the voltage down-converting activation signal ACT is at a low level in response.
When the power supply voltage EXTVcc reaches a prescribed voltage level at a time t2 and is determined to reach a voltage level for driving the internal circuit with no malfunction, the power-on detection signal ZPOR rises to a high level. Due to this rise of the power-on supply detection signal ZPOR, the output signal of the gate circuit 15a falls to a low level and the voltage down-converting activation signal ACT enters an active state of a high level. The internal voltage down-converting circuit 1b is activated in response, so that the comparator circuit performs a compare operation. Thus, the current 1c of the comparator circuit reaches a high value similar to that in a normal operation. When the power is applied while bringing the row address strobe signal /RAS into a low level and setting the DRAM in an active state, the internal voltage down-converting circuit 1b is activated in response to activation of the power-on detection signal ZPOR, to disadvantageously consume a large amount of current to increase the power consumption after the power-on.